Cypress Semiconductor /psoc63 /BLE /BLELL /SCAN_INTR

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Interpret as SCAN_INTR

Description

Scan interrupt status and Clear register

Fields

SCAN_STRT_INTR	If this bit is set it indicates scan window is opened. Write to the register with this bit set to 1, clears the interrupt source.
SCAN_CLOSE_INTR	If this bit is set it indicates scan window is closed. Write to the register with this bit set to 1, clears the interrupt source.
SCAN_TX_INTR	If this bit is set it indicates scan request packet is transmitted. Write to the register with this bit set to 1, clears the interrupt source.
ADV_RX_INTR	If this bit is set it indicates ADV packet received. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. Write to the register with this bit set to 1, clears the interrupt source. This interrupt is generated while active/passive scanning upon receiving adv packets. Note: Any ADV RX interrupt received after issuing SCAN_STOP command must be ignored and the ADVCH FIFO flushed.
SCAN_RSP_RX_INTR	If this bit is set it indicates SCAN_RSP packet is received. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. Write to the register with this bit set to 1, clears the interrupt source. NOTE: This interrupt is generated while active scanning upon receiving scan response packet.
ADV_RX_PEER_RPA_UNMCH_INTR	If this bit is set it indicates ADV packet received but the peer device Address is not match yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. Write to the register with this bit set to 1, clears the interrupt source. This interrupt is generated while active/passive scanning upon receiving adv packets.
ADV_RX_SELF_RPA_UNMCH_INTR	If this bit is set it indicates ADV_DIRECT packet received but the self device Resolvable Private Address is not resolved yet. Firmware can read the content of the packet from the INIT_SCN_ADV_RX_FIFO. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set. Write to the register with this bit set to 1, clears the interrupt source. This interrupt is generated while active/passive scanning upon receiving adv_direct packets.
SCANA_TX_ADDR_NOT_SET_INTR	If this bit is set it indicates that a valid ScanA RPA to be transmitted in SCAN_REQ packet in response to an ADV packet is not present in the resolving list Write to the register with this bit set to 1, clears the interrupt source. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.
SCAN_ON	Scan procedure status. 1 - scan procedure is active. 0 - scan procedure is not active.
PEER_ADDR_MATCH_PRIV_MISMATCH_INTR	If this bit is set it indicates that an Identity address is received from an initiator and matches an entry in the resolving list, but peer IRK is set and hence a corresponding RPA is expected from the initiator Write to the register with this bit set to 1, clears the interrupt source. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.
SELF_ADDR_MATCH_PRIV_MISMATCH_INTR	If this bit is set it indicates that the self Identity address is received from an initiator and matches, but self IRK is set and hence a corresponding RPA is expected from the initiator Write to the register with this bit set to 1, clears the interrupt source. This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.

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